Field of the Invention
The present invention relates to a computer implemented system and method for generating a layout of a cell defining a circuit component.
Description of the Prior Art
When producing integrated circuits, a number of process layers are formed on a substrate, each process layer incorporating a layout pattern. The layout patterns within the various layers establish component features and interconnections such that once the final process layer has been formed, an integrated circuit has been produced containing all of the required circuit components interconnected in the manner required to perform the functions of the integrated circuit.
For a new integrated circuit, a layout of that integrated circuit will be produced in the form of a data file identifying the required layout patterns for each of the process layers. To assist in the generation of such a layout, it is known to use cell libraries providing a plurality of different cells, each cell defining a layout for a particular component. Various types of cells are used in modern systems for generating integrated circuit layouts, for example standard cells, datapath cells, custom cells, cells representing portions of a memory device, etc. For the purposes of the following discussions, the standard cell example will be referred to.
A standard cell library will provide a plurality of standard cells, each standard cell defining a layout for a particular circuit component. The circuit components for which standard cells are developed are typically the basic building block components used to construct more complex circuits within the integrated circuit, and hence for example standard cells may be generated for AND gates, NAND gates, OR gates, NOR gates, inverters, flops, etc.
Once a standard cell library has been produced for a particular process technology, then the design of integrated circuits for that process technology can be simplified. For example, it is known to provide automated tools which use a functional design of a planned integrated circuit (for example in the form of a gate level net list or a Register Transfer Language (RTL) higher level representation of the design) and a standard cell library in order to generate the layout of the planned integrated circuit.
Typically, the standard cells are arranged in rows by the automated tool and (considering the rows as running horizontally) the left and right boundaries of each standard cell are such that any given standard cell may be placed next to any other given standard cell. Thus the automated tool has free choice as to which standard cells are placed where in order to fulfil the requirements of the functional design with a low routing overhead. This process is illustrated schematically in FIG. 13, which illustrates a portion 700 of an integrated circuit layout, the portion shown having three rows of a fixed row height 725. Each row comprises a series of blocks 720 with a fixed unit of width 730. Each standard cell in the standard cell library is arranged to have a height equal to the row height 725, and to have a width which can vary between cells but is a multiple of the unit width 730. Standard cells are then placed into each row having regards to the required circuit elements and connections between those circuit elements required by the integrated circuit, with the various standard cells arranged to abut against one another. For the purpose of illustration, three standard cells 740, 750, 760 are shown located within one of the rows.
For each type of component having an associated standard cell, it is often the case that multiple versions of the standard cell are produced to cover different forms of that component type. For example, considering a NAND gate, it will typically be the case that multiple standard cells will be produced to represent NAND gates having different drive strengths. As the drive strength increases, the width of the standard cell will typically become larger in order to accommodate the additional structures (for example additional gate fingers) that may be required to produce a NAND gate with the increased drive strength. Similarly, for other components such as flops, there may be a need to produce multiple different standard cells to represent the various variants of flops required, for example a scan flop, a non-scan flop, a reset flop, a non-reset flop, a retention flop, etc.
Accordingly, it will be appreciated that a large number of standard cells will typically need to be provided within the standard cell library for any particular process technology. For a different process technology, the standard cells will then need to be redesigned to ensure they conform to the design rules applicable to that process technology. With current process technologies, up to and including 20 nm technology, the design rules have been relatively straightforward, consisting essentially of an indication of the minimum width of a pattern feature, a minimum spacing between pattern features, and alignment/overlap rules used to ensure vias can be reliably produced interconnecting pattern features at different process layers. Due to the relatively simple nature of the design rules, it has been possible for the standard cells to be manually designed. Further, it has been a relatively straightforward exercise to develop additional standard cells to cover variants of a particular circuit component, such as different drive strengths NAND gates, different forms of flop, etc.
However, as the process technologies reduce below the 20 nm technology, for example in to the 14 nm domain, then the techniques used to develop each of the process layers become significantly more complex. For example, at each process layer, the number of processes required to perform the required layout patterns increases, as techniques such as double patterning are required to produce the layout pattern at such small process geometries. This results in the design rules becoming far more complicated than has traditionally been the case, setting out not only the three basic rules discussed earlier, but also requiring the specification of many different examples and exceptions. This has the result that the design of standard cells for emerging process technologies is becoming very complex. Further, at such process technologies it is no longer the case that a new variant of a particular component can readily be produced merely by a relatively simple modification to an existing standard cell. For example, whilst in current process technologies, the standard cell layout for a higher drive strength NAND gate may be readily produced by a relatively simple modification to the standard cell layout of a lower driver strength NAND gate, this is no longer the case in emerging process technologies such as 14 nm technology, and often the standard cell layouts will be very different for different variants of a particular component.
The above described problems associated with the generation of standard cells apply also to the generation of other types of cells.
Against this background, it would be desirable to provide a technique which enabled automation in the generation of cells that conform to the design rules of these emerging process technologies.